908 lines
23 KiB
Diff
908 lines
23 KiB
Diff
From 4de4213f698a5962f839f671e4dec247baa35d5b Mon Sep 17 00:00:00 2001
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From: Patryk Biel <patryk.biel.external@trumpf.com>
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Date: Wed, 25 Jan 2023 20:30:15 +0100
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Subject: [PATCH] Add device tree from master
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---
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arch/arm64/boot/dts/allwinner/Makefile | 1 +
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.../allwinner/sun50i-h616-orangepi-zero2.dts | 261 ++++++++
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.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 590 ++++++++++++++++++
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include/dt-bindings/clock/sun6i-rtc.h | 10 +
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4 files changed, 862 insertions(+)
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create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
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create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
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create mode 100644 include/dt-bindings/clock/sun6i-rtc.h
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diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
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index a96d9d2d8..471822f5f 100644
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--- a/arch/arm64/boot/dts/allwinner/Makefile
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+++ b/arch/arm64/boot/dts/allwinner/Makefile
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@@ -37,3 +37,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
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+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
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\ No newline at end of file
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
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new file mode 100644
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index 000000000..e92055145
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--- /dev/null
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
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@@ -0,0 +1,261 @@
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+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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+/*
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+ * Copyright (C) 2020 Arm Ltd.
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+ */
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+
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+/dts-v1/;
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+
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+#include "sun50i-h616.dtsi"
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+
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/leds/common.h>
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+
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+/ {
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+ model = "OrangePi Zero2";
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+ compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
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+
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+ aliases {
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+ ethernet0 = &emac0;
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+ serial0 = &uart0;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+
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+ led-0 {
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+ function = LED_FUNCTION_POWER;
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+ color = <LED_COLOR_ID_RED>;
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+ gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
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+ default-state = "on";
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+ };
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+
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+ led-1 {
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+ function = LED_FUNCTION_STATUS;
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
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+ };
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+ };
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+
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+ reg_vcc5v: vcc5v {
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+ /* board wide 5V supply directly from the USB-C socket */
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc-5v";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ regulator-always-on;
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+ };
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+
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+ reg_vcc33_wifi: vcc33-wifi {
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+ /* Always on 3.3V regulator for WiFi and BT */
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc33-wifi";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-always-on;
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+ vin-supply = <®_vcc5v>;
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+ };
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+
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+ reg_vcc_wifi_io: vcc-wifi-io {
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+ /* Always on 1.8V/300mA regulator for WiFi and BT IO */
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc-wifi-io";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-always-on;
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+ vin-supply = <®_vcc33_wifi>;
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+ };
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+
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+ wifi_pwrseq: wifi-pwrseq {
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+ compatible = "mmc-pwrseq-simple";
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+ clocks = <&rtc 1>;
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+ clock-names = "osc32k-out";
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+ reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
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+ post-power-on-delay-ms = <200>;
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+ };
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+};
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+
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+&emac0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&ext_rgmii_pins>;
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+ phy-mode = "rgmii";
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+ phy-handle = <&ext_rgmii_phy>;
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+ phy-supply = <®_dcdce>;
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+ allwinner,rx-delay-ps = <3100>;
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+ allwinner,tx-delay-ps = <700>;
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+ status = "okay";
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+};
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+
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+&mmc1 {
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+ vmmc-supply = <®_vcc33_wifi>;
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+ vqmmc-supply = <®_vcc_wifi_io>;
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+ mmc-pwrseq = <&wifi_pwrseq>;
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+ bus-width = <4>;
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+ non-removable;
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+ mmc-ddr-1_8v;
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+ status = "okay";
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+
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+ uwe-bsp {
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+ compatible = "unisoc,uwe_bsp";
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+ keep-power-on;
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+ data-irq;
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+ //adma-tx;
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+ adma-rx;
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+ //blksz-512;
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+ status = "okay";
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+ };
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+};
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+
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+&mdio0 {
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+ ext_rgmii_phy: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <1>;
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+ };
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+};
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+
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+&mmc0 {
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+ vmmc-supply = <®_dcdce>;
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+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
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+ bus-width = <4>;
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+ status = "okay";
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+};
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+
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+&r_rsb {
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+ status = "okay";
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+
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+ axp305: pmic@745 {
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+ compatible = "x-powers,axp305", "x-powers,axp805",
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+ "x-powers,axp806";
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+ reg = <0x745>;
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+
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+ x-powers,self-working-mode;
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+ vina-supply = <®_vcc5v>;
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+ vinb-supply = <®_vcc5v>;
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+ vinc-supply = <®_vcc5v>;
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+ vind-supply = <®_vcc5v>;
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+ vine-supply = <®_vcc5v>;
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+ aldoin-supply = <®_vcc5v>;
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+ bldoin-supply = <®_vcc5v>;
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+ cldoin-supply = <®_vcc5v>;
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+
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+ regulators {
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+ reg_aldo1: aldo1 {
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-name = "vcc-sys";
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+ };
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+
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+ reg_aldo2: aldo2 { /* 3.3V on headers */
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-name = "vcc3v3-ext";
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+ };
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+
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+ reg_aldo3: aldo3 { /* 3.3V on headers */
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-name = "vcc3v3-ext2";
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+ };
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+
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+ reg_bldo1: bldo1 {
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+ regulator-always-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-name = "vcc1v8";
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+ };
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+
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+ bldo2 {
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+ /* unused */
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+ };
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+
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+ bldo3 {
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+ /* unused */
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+ };
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+
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+ bldo4 {
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+ /* unused */
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+ };
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+
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+ cldo1 {
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+ /* reserved */
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+ };
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+
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+ cldo2 {
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+ /* unused */
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+ };
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+
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+ cldo3 {
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+ /* unused */
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+ };
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+
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+ reg_dcdca: dcdca {
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+ regulator-always-on;
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+ regulator-min-microvolt = <810000>;
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+ regulator-max-microvolt = <1100000>;
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+ regulator-name = "vdd-cpu";
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+ };
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+
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+ reg_dcdcc: dcdcc {
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+ regulator-always-on;
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+ regulator-min-microvolt = <810000>;
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+ regulator-max-microvolt = <990000>;
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+ regulator-name = "vdd-gpu-sys";
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+ };
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+
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+ reg_dcdcd: dcdcd {
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+ regulator-always-on;
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+ regulator-min-microvolt = <1500000>;
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+ regulator-max-microvolt = <1500000>;
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+ regulator-name = "vdd-dram";
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+ };
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+
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+ reg_dcdce: dcdce {
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+ regulator-always-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-name = "vcc-eth-mmc";
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+ };
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+
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+ sw {
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+ /* unused */
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+ };
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+ };
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+ };
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+};
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+
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+&pio {
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+ vcc-pc-supply = <®_aldo1>;
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+ vcc-pf-supply = <®_aldo1>;
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+ vcc-pg-supply = <®_bldo1>;
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+ vcc-ph-supply = <®_aldo1>;
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+ vcc-pi-supply = <®_aldo1>;
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+};
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+
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+&spi0 {
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+ status = "okay";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
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+
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+ flash@0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "jedec,spi-nor";
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+ reg = <0>;
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+ spi-max-frequency = <40000000>;
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+ };
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+};
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+
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+&uart0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart0_ph_pins>;
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+ status = "okay";
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+};
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
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new file mode 100644
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index 000000000..ab344ea8a
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--- /dev/null
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
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@@ -0,0 +1,590 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+// Copyright (C) 2020 Arm Ltd.
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+// based on the H6 dtsi, which is:
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+// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
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+
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/clock/sun50i-h616-ccu.h>
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+#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
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+#include <dt-bindings/clock/sun6i-rtc.h>
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+#include <dt-bindings/reset/sun50i-h616-ccu.h>
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+#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
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+
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+/ {
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+ interrupt-parent = <&gic>;
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ cpu0: cpu@0 {
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+ compatible = "arm,cortex-a53";
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+ device_type = "cpu";
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+ reg = <0>;
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+ enable-method = "psci";
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+ clocks = <&ccu CLK_CPUX>;
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+ };
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+
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+ cpu1: cpu@1 {
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+ compatible = "arm,cortex-a53";
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+ device_type = "cpu";
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+ reg = <1>;
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+ enable-method = "psci";
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+ clocks = <&ccu CLK_CPUX>;
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+ };
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+
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+ cpu2: cpu@2 {
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+ compatible = "arm,cortex-a53";
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+ device_type = "cpu";
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+ reg = <2>;
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+ enable-method = "psci";
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+ clocks = <&ccu CLK_CPUX>;
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+ };
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+
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+ cpu3: cpu@3 {
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+ compatible = "arm,cortex-a53";
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+ device_type = "cpu";
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+ reg = <3>;
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+ enable-method = "psci";
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+ clocks = <&ccu CLK_CPUX>;
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+ };
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+ };
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+
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+ reserved-memory {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ /*
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+ * 256 KiB reserved for Trusted Firmware-A (BL31).
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+ * This is added by BL31 itself, but some bootloaders fail
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+ * to propagate this into the DTB handed to kernels.
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+ */
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+ secmon@40000000 {
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+ reg = <0x0 0x40000000 0x0 0x40000>;
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+ no-map;
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+ };
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+ };
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+
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+ osc24M: osc24M-clk {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <24000000>;
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+ clock-output-names = "osc24M";
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+ };
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+
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+ pmu {
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+ compatible = "arm,cortex-a53-pmu";
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+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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+ };
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+
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+ psci {
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+ compatible = "arm,psci-0.2";
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+ method = "smc";
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+ };
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+
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+ timer {
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+ compatible = "arm,armv8-timer";
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+ arm,no-tick-in-suspend;
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+ interrupts = <GIC_PPI 13
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+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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+ <GIC_PPI 14
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+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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+ <GIC_PPI 11
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+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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+ <GIC_PPI 10
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+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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+ };
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+
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+ soc {
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+ compatible = "simple-bus";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0x0 0x0 0x0 0x40000000>;
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+
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+ syscon: syscon@3000000 {
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+ compatible = "allwinner,sun50i-h616-system-control";
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+ reg = <0x03000000 0x1000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+
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+ sram_c: sram@28000 {
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+ compatible = "mmio-sram";
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+ reg = <0x00028000 0x30000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0 0x00028000 0x30000>;
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+ };
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+ };
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+
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+ ccu: clock@3001000 {
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+ compatible = "allwinner,sun50i-h616-ccu";
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+ reg = <0x03001000 0x1000>;
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+ clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>;
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+ clock-names = "hosc", "losc", "iosc";
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+
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+ watchdog: watchdog@30090a0 {
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+ compatible = "allwinner,sun50i-h616-wdt",
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+ "allwinner,sun6i-a31-wdt";
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+ reg = <0x030090a0 0x20>;
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+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&osc24M>;
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+ };
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+
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+ pio: pinctrl@300b000 {
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+ compatible = "allwinner,sun50i-h616-pinctrl";
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+ reg = <0x0300b000 0x400>;
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+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
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+ clock-names = "apb", "hosc", "losc";
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+ gpio-controller;
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+ #gpio-cells = <3>;
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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|
+
|
|
+ ext_rgmii_pins: rgmii-pins {
|
|
+ pins = "PI0", "PI1", "PI2", "PI3", "PI4",
|
|
+ "PI5", "PI7", "PI8", "PI9", "PI10",
|
|
+ "PI11", "PI12", "PI13", "PI14", "PI15",
|
|
+ "PI16";
|
|
+ function = "emac0";
|
|
+ drive-strength = <40>;
|
|
+ };
|
|
+
|
|
+ i2c0_pins: i2c0-pins {
|
|
+ pins = "PI6", "PI7";
|
|
+ function = "i2c0";
|
|
+ };
|
|
+
|
|
+ i2c3_ph_pins: i2c3-ph-pins {
|
|
+ pins = "PH4", "PH5";
|
|
+ function = "i2c3";
|
|
+ };
|
|
+
|
|
+ ir_rx_pin: ir-rx-pin {
|
|
+ pins = "PH10";
|
|
+ function = "ir_rx";
|
|
+ };
|
|
+
|
|
+ mmc0_pins: mmc0-pins {
|
|
+ pins = "PF0", "PF1", "PF2", "PF3",
|
|
+ "PF4", "PF5";
|
|
+ function = "mmc0";
|
|
+ drive-strength = <30>;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ mmc1_pins: mmc1-pins {
|
|
+ pins = "PG0", "PG1", "PG2", "PG3",
|
|
+ "PG4", "PG5";
|
|
+ function = "mmc1";
|
|
+ drive-strength = <30>;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+
|
|
+ mmc2_pins: mmc2-pins {
|
|
+ pins = "PC0", "PC1", "PC5", "PC6",
|
|
+ "PC8", "PC9", "PC10", "PC11",
|
|
+ "PC13", "PC14", "PC15", "PC16";
|
|
+ function = "mmc2";
|
|
+ drive-strength = <30>;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ spi0_pins: spi0-pins {
|
|
+ pins = "PC0", "PC2", "PC4";
|
|
+ function = "spi0";
|
|
+ };
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ spi0_cs0_pin: spi0-cs0-pin {
|
|
+ pins = "PC3";
|
|
+ function = "spi0";
|
|
+ };
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ spi1_pins: spi1-pins {
|
|
+ pins = "PH6", "PH7", "PH8";
|
|
+ function = "spi1";
|
|
+ };
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ spi1_cs0_pin: spi1-cs0-pin {
|
|
+ pins = "PH5";
|
|
+ function = "spi1";
|
|
+ };
|
|
+
|
|
+ uart0_ph_pins: uart0-ph-pins {
|
|
+ pins = "PH0", "PH1";
|
|
+ function = "uart0";
|
|
+ };
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ uart1_pins: uart1-pins {
|
|
+ pins = "PG6", "PG7";
|
|
+ function = "uart1";
|
|
+ };
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ uart1_rts_cts_pins: uart1-rts-cts-pins {
|
|
+ pins = "PG8", "PG9";
|
|
+ function = "uart1";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gic: interrupt-controller@3021000 {
|
|
+ compatible = "arm,gic-400";
|
|
+ reg = <0x03021000 0x1000>,
|
|
+ <0x03022000 0x2000>,
|
|
+ <0x03024000 0x2000>,
|
|
+ <0x03026000 0x2000>;
|
|
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <3>;
|
|
+ };
|
|
+
|
|
+ mmc0: mmc@4020000 {
|
|
+ compatible = "allwinner,sun50i-h616-mmc",
|
|
+ "allwinner,sun50i-a100-mmc";
|
|
+ reg = <0x04020000 0x1000>;
|
|
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
|
|
+ clock-names = "ahb", "mmc";
|
|
+ resets = <&ccu RST_BUS_MMC0>;
|
|
+ reset-names = "ahb";
|
|
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&mmc0_pins>;
|
|
+ status = "disabled";
|
|
+ max-frequency = <150000000>;
|
|
+ cap-sd-highspeed;
|
|
+ cap-mmc-highspeed;
|
|
+ mmc-ddr-3_3v;
|
|
+ cap-sdio-irq;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ mmc1: mmc@4021000 {
|
|
+ compatible = "allwinner,sun50i-h616-mmc",
|
|
+ "allwinner,sun50i-a100-mmc";
|
|
+ reg = <0x04021000 0x1000>;
|
|
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
|
|
+ clock-names = "ahb", "mmc";
|
|
+ resets = <&ccu RST_BUS_MMC1>;
|
|
+ reset-names = "ahb";
|
|
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&mmc1_pins>;
|
|
+ status = "disabled";
|
|
+ max-frequency = <150000000>;
|
|
+ cap-sd-highspeed;
|
|
+ cap-mmc-highspeed;
|
|
+ mmc-ddr-3_3v;
|
|
+ cap-sdio-irq;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ mmc2: mmc@4022000 {
|
|
+ compatible = "allwinner,sun50i-h616-emmc",
|
|
+ "allwinner,sun50i-a100-emmc";
|
|
+ reg = <0x04022000 0x1000>;
|
|
+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
|
|
+ clock-names = "ahb", "mmc";
|
|
+ resets = <&ccu RST_BUS_MMC2>;
|
|
+ reset-names = "ahb";
|
|
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&mmc2_pins>;
|
|
+ status = "disabled";
|
|
+ max-frequency = <150000000>;
|
|
+ cap-sd-highspeed;
|
|
+ cap-mmc-highspeed;
|
|
+ mmc-ddr-3_3v;
|
|
+ cap-sdio-irq;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ uart0: serial@5000000 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x05000000 0x400>;
|
|
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ clocks = <&ccu CLK_BUS_UART0>;
|
|
+ resets = <&ccu RST_BUS_UART0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart1: serial@5000400 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x05000400 0x400>;
|
|
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ clocks = <&ccu CLK_BUS_UART1>;
|
|
+ resets = <&ccu RST_BUS_UART1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart2: serial@5000800 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x05000800 0x400>;
|
|
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ clocks = <&ccu CLK_BUS_UART2>;
|
|
+ resets = <&ccu RST_BUS_UART2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart3: serial@5000c00 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x05000c00 0x400>;
|
|
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ clocks = <&ccu CLK_BUS_UART3>;
|
|
+ resets = <&ccu RST_BUS_UART3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart4: serial@5001000 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x05001000 0x400>;
|
|
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ clocks = <&ccu CLK_BUS_UART4>;
|
|
+ resets = <&ccu RST_BUS_UART4>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart5: serial@5001400 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x05001400 0x400>;
|
|
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ clocks = <&ccu CLK_BUS_UART5>;
|
|
+ resets = <&ccu RST_BUS_UART5>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c0: i2c@5002000 {
|
|
+ compatible = "allwinner,sun50i-h616-i2c",
|
|
+ "allwinner,sun8i-v536-i2c",
|
|
+ "allwinner,sun6i-a31-i2c";
|
|
+ reg = <0x05002000 0x400>;
|
|
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2C0>;
|
|
+ resets = <&ccu RST_BUS_I2C0>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c0_pins>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ i2c1: i2c@5002400 {
|
|
+ compatible = "allwinner,sun50i-h616-i2c",
|
|
+ "allwinner,sun8i-v536-i2c",
|
|
+ "allwinner,sun6i-a31-i2c";
|
|
+ reg = <0x05002400 0x400>;
|
|
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2C1>;
|
|
+ resets = <&ccu RST_BUS_I2C1>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ i2c2: i2c@5002800 {
|
|
+ compatible = "allwinner,sun50i-h616-i2c",
|
|
+ "allwinner,sun8i-v536-i2c",
|
|
+ "allwinner,sun6i-a31-i2c";
|
|
+ reg = <0x05002800 0x400>;
|
|
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2C2>;
|
|
+ resets = <&ccu RST_BUS_I2C2>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ i2c3: i2c@5002c00 {
|
|
+ compatible = "allwinner,sun50i-h616-i2c",
|
|
+ "allwinner,sun8i-v536-i2c",
|
|
+ "allwinner,sun6i-a31-i2c";
|
|
+ reg = <0x05002c00 0x400>;
|
|
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2C3>;
|
|
+ resets = <&ccu RST_BUS_I2C3>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ i2c4: i2c@5003000 {
|
|
+ compatible = "allwinner,sun50i-h616-i2c",
|
|
+ "allwinner,sun8i-v536-i2c",
|
|
+ "allwinner,sun6i-a31-i2c";
|
|
+ reg = <0x05003000 0x400>;
|
|
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2C4>;
|
|
+ resets = <&ccu RST_BUS_I2C4>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ spi0: spi@5010000 {
|
|
+ compatible = "allwinner,sun50i-h616-spi",
|
|
+ "allwinner,sun8i-h3-spi";
|
|
+ reg = <0x05010000 0x1000>;
|
|
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
|
|
+ clock-names = "ahb", "mod";
|
|
+ resets = <&ccu RST_BUS_SPI0>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ spi1: spi@5011000 {
|
|
+ compatible = "allwinner,sun50i-h616-spi",
|
|
+ "allwinner,sun8i-h3-spi";
|
|
+ reg = <0x05011000 0x1000>;
|
|
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
|
|
+ clock-names = "ahb", "mod";
|
|
+ resets = <&ccu RST_BUS_SPI1>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ emac0: ethernet@5020000 {
|
|
+ compatible = "allwinner,sun50i-h616-emac0",
|
|
+ "allwinner,sun50i-a64-emac";
|
|
+ reg = <0x05020000 0x10000>;
|
|
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "macirq";
|
|
+ clocks = <&ccu CLK_BUS_EMAC0>;
|
|
+ clock-names = "stmmaceth";
|
|
+ resets = <&ccu RST_BUS_EMAC0>;
|
|
+ reset-names = "stmmaceth";
|
|
+ syscon = <&syscon>;
|
|
+ status = "disabled";
|
|
+
|
|
+ mdio0: mdio {
|
|
+ compatible = "snps,dwmac-mdio";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ rtc: rtc@7000000 {
|
|
+ compatible = "allwinner,sun50i-h616-rtc",
|
|
+ "allwinner,sun50i-h6-rtc";
|
|
+ reg = <0x07000000 0x400>;
|
|
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clock-output-names = "osc32k", "osc32k-out", "iosc";
|
|
+ #clock-cells = <1>;
|
|
+ };
|
|
+
|
|
+ r_ccu: clock@7010000 {
|
|
+ compatible = "allwinner,sun50i-h616-r-ccu";
|
|
+ reg = <0x07010000 0x210>;
|
|
+ clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
|
|
+ <&ccu CLK_PLL_PERIPH0>;
|
|
+ clock-names = "hosc", "losc", "iosc", "pll-periph";
|
|
+ #clock-cells = <1>;
|
|
+ #reset-cells = <1>;
|
|
+ };
|
|
+
|
|
+ r_pio: pinctrl@7022000 {
|
|
+ compatible = "allwinner,sun50i-h616-r-pinctrl";
|
|
+ reg = <0x07022000 0x400>;
|
|
+ clocks = <&r_ccu CLK_R_APB1>, <&osc24M>,
|
|
+ <&rtc CLK_OSC32K>;
|
|
+ clock-names = "apb", "hosc", "losc";
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <3>;
|
|
+
|
|
+ /omit-if-no-ref/
|
|
+ r_i2c_pins: r-i2c-pins {
|
|
+ pins = "PL0", "PL1";
|
|
+ function = "s_i2c";
|
|
+ };
|
|
+
|
|
+ r_rsb_pins: r-rsb-pins {
|
|
+ pins = "PL0", "PL1";
|
|
+ function = "s_rsb";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ir: ir@7040000 {
|
|
+ compatible = "allwinner,sun50i-h616-ir",
|
|
+ "allwinner,sun6i-a31-ir";
|
|
+ reg = <0x07040000 0x400>;
|
|
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&r_ccu CLK_R_APB1_IR>,
|
|
+ <&r_ccu CLK_IR>;
|
|
+ clock-names = "apb", "ir";
|
|
+ resets = <&r_ccu RST_R_APB1_IR>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&ir_rx_pin>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ r_i2c: i2c@7081400 {
|
|
+ compatible = "allwinner,sun50i-h616-i2c",
|
|
+ "allwinner,sun8i-v536-i2c",
|
|
+ "allwinner,sun6i-a31-i2c";
|
|
+ reg = <0x07081400 0x400>;
|
|
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&r_ccu CLK_R_APB2_I2C>;
|
|
+ resets = <&r_ccu RST_R_APB2_I2C>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ r_rsb: rsb@7083000 {
|
|
+ compatible = "allwinner,sun50i-h616-rsb",
|
|
+ "allwinner,sun8i-a23-rsb";
|
|
+ reg = <0x07083000 0x400>;
|
|
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&r_ccu CLK_R_APB2_RSB>;
|
|
+ clock-frequency = <3000000>;
|
|
+ resets = <&r_ccu RST_R_APB2_RSB>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&r_rsb_pins>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h
|
|
new file mode 100644
|
|
index 000000000..c845493e4
|
|
--- /dev/null
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+++ b/include/dt-bindings/clock/sun6i-rtc.h
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@@ -0,0 +1,10 @@
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+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
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+
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+#ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_
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+#define _DT_BINDINGS_CLK_SUN6I_RTC_H_
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+
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+#define CLK_OSC32K 0
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+#define CLK_OSC32K_FANOUT 1
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+#define CLK_IOSC 2
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+
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+#endif /* _DT_BINDINGS_CLK_SUN6I_RTC_H_ */
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--
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2.34.1
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